1. Field of the Invention
The present invention relates to a semiconductor memory device suitably implemented by an EPROM (Erasable Programmable Read-Only Memory), an EEPROM (Electrically Erasable and Programmable Read-Only Memory) or the like and using as a memory cell a transistor having a floating gate, and a method of writing and reading out information for the semiconductor memory device.
2. Description of the Prior Art
A transistor, which has a structure shown in FIG. 10, having a floating gate has been conventionally applied to a memory cell of an electrically programable ROM (Read-Only Memory) such as an EPROM or an EEPROM. More specifically, an n.sup.+ -type impurity region having a high concentration is provided on a p-type semiconductor substrate 1 to form a source region 2 and a drain region 3, a floating gate 5 electrically insulated from the semiconductor substrate 1 is formed on the surface of the semiconductor substrate 1 between the source region 2 and the drain region 3 with an insulation film 4 being interposed therebetween, and a control gate 7 is further formed on the floating gate 5 with an insulation film 6 being interposed therebetween.
When positive high voltages are respectively applied to the control gate 7 and the drain region 3 and the source region 2 is grounded to cause a current to flow between the source and the drain, hot electrons are produced in an end 3A of the drain region 3. The hot electrons pass through the insulation film 4 to be injected into the floating gate 5. Information is thus written.
The profile of the impurity concentration of a diffusion layer constituting the drain region 3 is rapidly changed in the boundary between the drain region 3 and a channel region 8. Consequently, a strong electric field is formed in the boundary between the channel region 8 and the drain region 3, so that hot electrons are easily generated.
When information is read out, the source region 2 is grounded and a predetermined positive voltage (for example, 2 volts) is applied to the drain region 3. In this state, a predetermined sense voltage is applied to the control gate 7. A threshold voltage Vth for allowing conduction between the source and the drain differs depending on the state of the floating gate 5. That is, the threshold voltage Vth is increased in a state where electrons are injected into the floating gate 5, while being decreased in a state where no electrons are injected. Therefore, the above-mentioned sense voltage is set to a voltage between the high threshold voltage and the low threshold voltage. The sense voltage is applied to the control gate 7, to watch whether or not conduction occurs between the source and the drain. If conduction occurs between the source and the drain, no electrons are injected into the floating gate 5, so that information stored in the memory cell is "0", for example. On the other hand, if no conduction occurs between the source and the drain, electrons are injected into the floating gate 5, so that information stored in the memory cell is "1". Information stored in the memory cell can be thus read out.
Stored information can be erased by irradiating ultraviolet rays to disperse the electrons in the floating gate 5 as well as by grounding the control gate 7 and applying a positive high voltage to the source region 2 to cause F-N tunneling of the electrons in the floating gate 5 into the source region 2.
Meanwhile, in the conventional memory cell, the impurity concentration of the drain region 3 is rapidly changed in the boundary between the drain region 3 and the channel region 8 so as to increase the production efficiency of hot electrons. The conventional memory cell has a structure in which hot electrons are very easily generated. Accordingly, trace amounts of hot electrons are generated even by a low voltage applied to the drain region 3 at the time of reading. Consequently, every time information is read out from the memory cell, trace amounts of hot electrons produced in the end 3A of the drain region 3 are injected into the floating gate 5. As a result, the threshold voltage Vth of the transistor is gradually changed. Such a phenomenon is generally referred to as soft writing.
FIG. 11 is a graph showing soft writing characteristics, which shows the results of measurement made taking as lifetime a time period during which the change of the threshold voltage Vth is kept at not more than 10 percent in a state where a read voltage V.sub.D is continuously applied to the drain region 3. Curves L1, L2, and L3 respectively correspond to cases where the gate length is set to 0.9 .mu.m, 0.8 .mu.m, and 0.7 .mu.m. It is understood from FIG. 11 that the higher the read voltage V.sub.D is, the shorter the lifetime is. For example, assuming that it is required as resistance to soft writing that the shift of the threshold voltage Vth is not more than 10 percent in a continuously reading state over ten years, the read voltage V.sub.D must be suppressed to not more than 1.2 volts in the case of a cell having a gate length of 0.8 .mu.m.
Since the voltage V.sub.D applied to the drain region 3 cannot be thus significantly increased at the time of reading, there is a limit on a read current of the memory cell. Therefore, the reading speed is prevented from being increased.